Senior Technical Architect
HCLTech · São Paulo, SP, BR
Senior Technical Architect Sao Paulo, São Paulo **Job Summary** --------------- **Physical Design CAD Support Engineer** to support and optimize Physical Design EDA tools and flows for advanced silicon programs. Responsible for troubleshooting complex tool and methodology issues, providing Tier 2/3 support, and driving improvements in flow stability, automation, and design productivity. Strong expertise in **Synopsys Fusion Compiler, PrimeTime, and Cadence Innovus** **Key Responsibilities** ------------------------ ### **Physical Design Tool \& Flow Support** * Provide Tier 2 and Tier 3 support for Physical Design engineers across backend implementation and signoff flows. * Support, maintain, and troubleshoot Physical Design methodologies, CAD infrastructure, and EDA tool environments. * Investigate and resolve complex tool, flow, runtime, and design convergence issues impacting project schedules. * Diagnose and debug failures related to floorplanning, placement, clock tree synthesis, routing, timing closure, physical verification, and signoff. * Work directly with design teams to understand issues, reproduce failures, and drive resolution. ### **EDA Tool Expertise** * Act as a subject matter expert for Synopsys and Cadence Physical Design tools. * Provide support for: * Synopsys Fusion Compiler (FC) * Synopsys PrimeTime (PT) * Cadence Innovus * Siemens Calibre (Physical Verification \& Signoff) * Analyze tool behavior, log files, databases, and performance bottlenecks to determine root causes. * Engage with EDA vendors on tool defects, enhancement requests, and patch validations. ### **Debugging, Root Cause Analysis \& Issue Resolution** * Perform detailed debugging of CAD flow failures and design\-tool issues. * Conduct root cause analysis for recurring flow and methodology problems. * Drive corrective and preventive actions to improve overall flow robustness. * Develop workarounds and permanent fixes for tool and methodology issues. * Create troubleshooting guides and knowledge\-base documentation for common issues. ### **CAD Flow Development \& Automation** * Develop and enhance Physical Design CAD flows and methodologies. * Create automation solutions using TCL, Python, Shell scripting, and workflow automation frameworks. * Improve flow reliability, scalability, and runtime efficiency through automation and continuous improvements. * Support tool deployment, release qualification, and regression validation activities. ### **Cross\-functional Collaboration** * Partner with Physical Design, STA, DFT, CAD Methodology, and Silicon Engineering teams. * Support project execution by ensuring stable and efficient implementation flows. * Mentor junior engineers on debugging methodologies and CAD best practices. Contribute to strategic improvements in CAD infrastructure and design methodologies. **Skill Requirements** ---------------------- **Key Skills** -------------- Fusion Compiler \| PrimeTime \| Innovus \| Siemens Calibre \| Physical Design \| CAD Flow Support \| EDA Tools \| Root Cause Analysis \| Flow Debugging \| Tier 2 Support \| Tier 3 Support \| Physical Verification \| TCL \| Python \| Linux \| Semiconductor CAD Methodology **Required Qualifications** --------------------------- * Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline. * 7\+ years of experience in Physical Design, CAD Engineering, or EDA Tool Support. * Strong hands\-on expertise with: Synopsys Fusion Compiler, Synopsys PrimeTime, Cadence Innovus, Siemens Calibre. * Deep understanding of Physical Design implementation flows and timing closure methodologies. * Strong TCL, Python, and Linux scripting skills. * Proven experience troubleshooting complex EDA tool and flow issues. * Experience providing Tier 2/Tier 3 customer or engineering support. * Excellent analytical, debugging, communication, and problem\-solving skills. **Preferred Qualifications** ---------------------------- * Experience with advanced\-node designs (7nm, 5nm, 3nm, or below). * Knowledge of low\-power methodologies, UPF, EM/IR, and physical verification flows. * Experience supporting enterprise CAD environments and distributed compute infrastructures. * Familiarity with CI/CD, regression frameworks, and automated flow validation. * Experience working directly with Synopsys and Cadence support organizations. **Other Requirements** ----------------------